In conventional approaches, after process completion, Integrated Circuits (ICs) can have a visual on-chip pattern to determine their original position on a wafer. This pattern is a label usually referring to a row/column (R/C) identifier (or sometimes some type of serial number scheme) made in a 1X contact layer mask (e.g., 1st metal or nitride layer). With this method, the wafer die position is retrieved by a visual inspection under microscope. These visual methods, including X-rays, may be problematic to maintain a full traceability system of the IC, especially in the case where the dies are coated with opaque material or subsequently assembled in lidded packages. The package cover or lid (e.g., metal or dielectric) or over-molding compound of these packages precludes easy reading. Furthermore, it is also extremely difficult and costly to setup a high volume pick and place and marking process at the assembly level that allows the reprint of known good die identifiers on the top of the packages. Therefore, only the part number and lot code are usually printed, and the die position is lost at this assembly process step and full traceability is broken.
It would be desirable to implement an electrically measurable on-chip IC identifier. It would also be desirable to implement an on-chip identifier with a value that may be measured electrically, for example, by direct probing.